实验 7 4*4 键盘扫描控制器
1 实验务说明：
设计实现 4*4 键盘扫描控制电路判断键数码显示
键值通蜂鸣器发出键音
求：
l 键值采 16 进制编码 16 键分应显示 16 进制数 0~F键
应关系：面行左右次 0~3第二行左右次 4~7第三行左右次 8~B面行左右次 C~F中 bd 显示写字母写
l 键时显示前键值保持直键时更新显示
l 键时蜂鸣器发出键音放开蜂鸣器发声
l 选做：键应键音
2 实验设计思路
实验分4部分分顶层分频器（扫描时钟分频器蜂鸣器提供频率分频器）数码译码电路扫描信号发生电路顶层利状态机实现状态转移s0>s1>s2>s3>s0分应扫描col[0>3>0]时row信号转化时钟信号clock_change键输出1没输出0时钟设计时序逻辑clock_change升更新tempSegin（传递数码输入信号）choose（传递蜂鸣器分频器输入信号）输出sound信号时蜂鸣器输出信号clock_change信号相达次键盘蜂鸣器发声数码显示目
3 源程序：
1) 分频器
扫描时钟分频器：
LIBRARY IEEE
USE IEEESTD_LOGIC_1164ALL
USE IEEESTD_LOGIC_UNSIGNEDALL
USE IEEESTD_LOGIC_ARITHALL
entity divide is
divide the frequency to 1n
generic( nnatural200)
port( clk in std_logic
clk_out out std_logic)
end divide
architecture div_arch of divide is
temporary signal
signal temp std_logic
begin
process( clk )
count variable count from 0 to n21
means every n2 period reverse the clk
variable count integer range 0 to n21
begin
if (clk＇event and clk＇1＇) then
if( count n21) then
temp < not temp
count 0
else
count count + 1
end if
end if
end process
clk_out < temp
end div_arch
蜂鸣器提供频率分频器
LIBRARY IEEE
USE IEEESTD_LOGIC_1164ALL
USE IEEESTD_LOGIC_UNSIGNEDALL
USE IEEESTD_LOGIC_ARITHALL
entity divide_sound is
the origin clk is 50MHz
divide the frequency to 1n
generic( n0natural4
n1natural8
n2natural12
n3natural16
n4natural20
n5natural24
n6natural28
n7natural42
n8natural46
n9natural50
n10natural54
n11natural58
n12natural62
n13natural66
n14natural70
n15natural74
)
port( clk in std_logic
choose in integer range 0 to 15
sound_out out std_logic
)
end divide_sound
architecture div_arch of divide_sound is
temporary signal
signal temp std_logic
begin
process( clk )
count variable count from 0 to n21
means every n2 period reverse the clk
variable count integer range 0 to 100
variable ninteger range 0 to 200
count＇max is over the n(max)2 1
begin
case choose is
when 0 >n n0
when 1 >n n1
when 2 >n n2
when 3 >n n3
when 4 >n n4
when 5 >n n5
when 6 >n n6
when 7 >n n7
when 8 >n n8
when 9 >n n9
when 10 >n n10
when 11 >n n11
when 12 >n n12
when 13 >n n13
when 14 >n n14
when 15 >n n15
when others > n n0
end case
if(clk＇event and clk＇1＇) then
if( count n2 1) then
temp < not temp
count 0
else
count count + 1
end if
end if
end process
sound_out < temp
end div_arch
2) 扫描信号发生电路
LIBRARY IEEE
USE IEEESTD_LOGIC_1164ALL
USE IEEESTD_LOGIC_ARITHALL
USE IEEESTD_LOGIC_UNSIGNEDALL
entity scan_seq is
produce the column scan signal
port( clkreset in std_logic
col out std_logic_vector(3 downto 0)
)
end scan_seq
architecture arch of scan_seq is
begin
process(clk)
variable count integer range 0 to 3
M4 counterevery count output the porper impulse
begin
if( reset ＇1＇)then
count 0
elsif( clk＇event and clk＇1＇ )then
if( count 3)then
count 0
else
count count +1
end if
end if
case count is
when 0 > col<1110
when 1 > col<1101
when 2 > col<1011
when 3 > col<0111
end case
end process
end arch
3) 数码译码电路
LIBRARY IEEE
USE IEEESTD_LOGIC_1164ALL
USE IEEESTD_LOGIC_ARITHALL
USE IEEESTD_LOGIC_UNSIGNEDALL
ENTITY seg7_1H IS seg7 decoding
PORT(
a IN STD_LOGIC_VECTOR(3 DOWNTO 0) input
b OUT STD_LOGIC_VECTOR(6 DOWNTO 0) output
cat OUT STD_LOGIC_VECTOR(7 DOWNTO 0) selcect
)
END seg7_1H
ARCHITECTURE aa OF seg7_1H IS
signal temp std_logic_vector(3 downto 0)
BEGIN
process(a)
begin
CASE a IS b60 > abcdefg
WHEN 0000 > b < 1111110 0
WHEN 0001 > b < 0110000 1
WHEN 0010 > b < 1101101 2
WHEN 0011 > b < 1111001 3
WHEN 0100 > b < 0110011 4
WHEN 0101 > b < 1011011 5
WHEN 0110 > b < 1011111 6
WHEN 0111 > b < 1110000 7
WHEN 1000 > b < 1111111 8
WHEN 1001 > b < 1111011 9
WHEN 1010 > b < 1110111 A
WHEN 1011 > b < 0011111 b
WHEN 1100 > b < 1001110 C
WHEN 1101 > b < 0111101 d
WHEN 1110 > b < 1001111 E
WHEN 1111 > b < 1000111 F
WHEN others > b < 0000000 others
END CASE
end process
cat < 11111110
END aa
4) 顶层
LIBRARY IEEE
USE IEEESTD_LOGIC_1164ALL
USE IEEESTD_LOGIC_ARITHALL
USE IEEESTD_LOGIC_UNSIGNEDALL
entity scanKeyboard is
scan the keyboard and display sound at the same time
port(
clkreset in std_logic
row in std_logic_vector(3 downto 0)
col out std_logic_vector(3 downto 0)
sound out std_logic
b out std_logic_vector(6 downto 0)
cat out std_logic_vector(7 downto 0)
seeclk out std_logic
)
end scanKeyboard
architecture arch of scanKeyboard is
component divide_sound is
the origin clk is 50MHz
divide the frequency to 1n
generic( n0natural4
n1natural8
n2natural12
n3natural16
n4natural20
n5natural24
n6natural28
n7natural42
n8natural46
n9natural50
n10natural54
n11natural58
n12natural62
n13natural66
n14natural70
n15natural74
)
port( clk in std_logic
choose in integer range 0 to 15
sound_out out std_logic
)
end component
component scan_seq is
produce the column scan signal
port( clkreset in std_logic
col out std_logic_vector(3 downto 0)
)
end component
component seg7_1H IS seg7 decoding
PORT(
a IN STD_LOGIC_VECTOR(3 DOWNTO 0) input
b OUT STD_LOGIC_VECTOR(6 DOWNTO 0) output
cat OUT STD_LOGIC_VECTOR(7 DOWNTO 0) selcect
)
END component
component divide is
divide the frequency to 1n
generic( nnatural200)
port( clk in std_logic
clk_out out std_logic)
end component
clk_scan is the scan signal for column
tempSound is the output of the sound divider
tempSegin is the input of the seg7 translate part
clock_change is disgned to record the row＇s impulse appear
choose is the select of the keyboard
signal clk_scan std_logic
signal tempSoundstd_logic
signal tempSeginstd_logic_vector(3 downto 0)
signal clock_changestd_logic
signal choose integer range 0 to 15
type state is (s0s1s2s3)
signal presentstate nextstate state
begin
u0divide_sound port map(clk > clkchoose>choosesound_out>tempSound)
u1divide port map(clk >clk clk_out>clk_scan)
u2scan_seq port map(clk>clk_scanreset>resetcol>col)
u3seg7_1H port map(a>tempSeginb>bcat>cat)
discrible the register for clk_scan
p1_regprocess(clk_scanreset)
begin
if(reset ＇1＇)then
presentstate< s0
elsif( clk_scan＇event and clk_scan＇1＇ )then
presentstate< nextstate
end if
end process
discrible the state for clk_scan
p2_stateChangeprocess(presentstate)
begin
case presentstate is
when s0 > nextstate< s1
when s1 > nextstate< s2
when s2 > nextstate< s3
when s3 > nextstate< s0
end case
end process
discrible the output
p3_outprocess(presentstaterowclock_change)
begin
behave synchronize with the clock_change
if( clock_change＇event and clock_change ＇1＇)then
case presentstate is
column[0]
when s0 > case row is
when 1110>
choose < 12
tempSegin < 1100
when 1101>
choose < 8
tempSegin < 1000
when 1011>
choose < 4
tempSegin < 0100
when 0111>
choose < 0
tempSegin < 0000
when others>
choose < 0
tempSegin < tempSegin
end case
column[1]
when s1 > case row is
when 1110>
choose < 13
tempSegin < 1101
when 1101>
choose < 9
tempSegin < 1001
when 1011>
choose < 5
tempSegin < 0101
when 0111>
choose < 1
tempSegin < 0001
when others >
choose < 0
tempSegin < tempSegin
end case
column[2]
when s2 > case row is
when 1110>
choose < 14
tempSegin < 1110
when 1101>
choose < 10
tempSegin < 1010
when 1011>
choose < 6
tempSegin < 0110
when 0111>
choose < 2
tempSegin < 0010
when others>
choose < 0
tempSegin < tempSegin
end case
column[3]
when s3 > case row is
when 1110>
choose < 15
tempSegin < 1111
when 1101>
choose < 11
tempSegin < 1011
when 1011>
choose < 7
tempSegin < 0111
when 0111>
choose < 3
tempSegin < 0011
when others>
choose < 0
tempSegin < tempSegin
end case
end case
end if
end process
discrible clkchange
p3_clkchangeprocess(row)
begin
if( row 1111)then
clock_change <＇0＇
else
clock_change<＇1＇
end if
end process
output the sound signal
sound < tempSound and clock_change
to see the clock_change in waveform
seeclk < clock_change
end arch
4 仿真波形分析
1) 分频器1（扫描时钟分频器）
图11分频器整体
图12 分频器计数99翻转（高翻低）
图13 分频器计数99翻转（低翻高）
实际应采分频50k现仿真时方便仿真取200分频图11整体分频情况图12分频器计数99时高电翻低电图13分频器计数99时低电翻高电
2) 分频器2（蜂鸣器提供频率分频器）
图21（a） 分频器整体图
图21（b）分频器整体图
图21（c）分频器整体图
图22（a） 分频器细节图n950
图22（b） 分频器细节图n950
仿真时扫描时钟信号200分频时钟信号蜂鸣器提供信号分频系数实际分频系数图21（a）（b）输出信号频率受输入choose信号控制choose增输出信号分频越设计符号先取中状态进行说明choose9nn950应计数器应记24然实现翻转图22（a）计数信号计数001100024实现低电翻高电图22（b）计数信号计数0011000实现高电翻低电完成控分频器
3) 扫描信号发生电路
图31扫描信号细节图
图32 扫描信号reset发生
图4知红框中序脉周期countcol输出应关系
count
col[i]0中i取值
00
0
01
1
10
2
11
3
实现序负脉发生器功时reset信号加入时count重新00开始计数序脉col[0]开始输出低电
4) 数码译码电路
图41（a）数码译码波形图
图42（b）数码译码波形图
图41（a）译码电路09译码说已较熟悉赘述现选取1015进行说明数码结构图图43示a101010应输出写A应abcefg应点亮d熄灭波形图中见输出b1110111设计相应a101111应输出写b应ab熄灭余点亮波形图中见b0011111设计相应a1100应输出写C应bcg熄灭余点亮波形图见b1001110设计相应
a1101应输出写d应af熄灭余点亮波形图见b0111101设计相应a1110时应输出写E应bc熄灭波形图见b1001111设计相应a1111时应输出写F应bcd熄灭波形图见b1000111设计相应波形图应译码起表示表1中位选信号catcat[0]显示位数码
图43 数码部结构图
表1：
计数信号
数码显示控制信号
0000
1111110
0001
0110000
0010
1101101
0011
1111001
0100
0110011
0101
1011011
0110
1011111
0111
1110000
1000
1111111
1001
1111011
1010
1110111
1011
0011111
1100
1001110
1101
0111101
1110
1001111
1111
1000111
5) 综合
图51 整体波形图
图52（a）整体波形图细节reset
图52（b）整体波形图细节（键1）
图52（c）整体波形图细节（键6）
图52（d）整体波形图细节（键910数码保持次）
图52（e）整体波形图细节（键12连续键）
图51键进行仿真（键0>15）整体出应键应tempSegin保障数码输出前键应值时12连续键波形图中时tempSegin持续12
图52（b）col[1]0row[3]0时应键1时输出蜂鸣器键相宽度信号时译码电路传入tempSegin1次键前保持tempSegin1时b01100001应译码
图53（c）col[2]0row[2]0时应键6时输出蜂鸣器键宽度相信号时频率键频率区时译码电路传入tempSegin6次键前保持tempSegin6时b10111116应译码
图54（d）键9时数码译码电路输入tempSeg9保持次键10
图54（e）键12连续时直数码译码电路输入 tempSeg12时直蜂鸣器输出相频率信号直键松开输出蜂鸣器信号保持数码显示信号
实验5点阵载验证图
— END —
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1 实验务说明：
设计实现 4*4 键盘扫描控制电路判断键数码显示
键值通蜂鸣器发出键音
求：
l 键值采 16 进制编码 16 键分应显示 16 进制数 0~F键
应关系：面行左右次 0~3第二行左右次 4~7第三行左右次 8~B面行左右次 C~F中 bd 显示写字母写
l 键时显示前键值保持直键时更新显示
l 键时蜂鸣器发出键音放开蜂鸣器发声
l 选做：键应键音
2 实验设计思路
实验分4部分分顶层分频器（扫描时钟分频器蜂鸣器提供频率分频器）数码译码电路扫描信号发生电路顶层利状态机实现状态转移s0>s1>s2>s3>s0分应扫描col[0>3>0]时row信号转化时钟信号clock_change键输出1没输出0时钟设计时序逻辑clock_change升更新tempSegin（传递数码输入信号）choose（传递蜂鸣器分频器输入信号）输出sound信号时蜂鸣器输出信号clock_change信号相达次键盘蜂鸣器发声数码显示目
3 源程序：
1) 分频器
扫描时钟分频器：
LIBRARY IEEE
USE IEEESTD_LOGIC_1164ALL
USE IEEESTD_LOGIC_UNSIGNEDALL
USE IEEESTD_LOGIC_ARITHALL
entity divide is
divide the frequency to 1n
generic( nnatural200)
port( clk in std_logic
clk_out out std_logic)
end divide
architecture div_arch of divide is
temporary signal
signal temp std_logic
begin
process( clk )
count variable count from 0 to n21
means every n2 period reverse the clk
variable count integer range 0 to n21
begin
if (clk＇event and clk＇1＇) then
if( count n21) then
temp < not temp
count 0
else
count count + 1
end if
end if
end process
clk_out < temp
end div_arch
蜂鸣器提供频率分频器
LIBRARY IEEE
USE IEEESTD_LOGIC_1164ALL
USE IEEESTD_LOGIC_UNSIGNEDALL
USE IEEESTD_LOGIC_ARITHALL
entity divide_sound is
the origin clk is 50MHz
divide the frequency to 1n
generic( n0natural4
n1natural8
n2natural12
n3natural16
n4natural20
n5natural24
n6natural28
n7natural42
n8natural46
n9natural50
n10natural54
n11natural58
n12natural62
n13natural66
n14natural70
n15natural74
)
port( clk in std_logic
choose in integer range 0 to 15
sound_out out std_logic
)
end divide_sound
architecture div_arch of divide_sound is
temporary signal
signal temp std_logic
begin
process( clk )
count variable count from 0 to n21
means every n2 period reverse the clk
variable count integer range 0 to 100
variable ninteger range 0 to 200
count＇max is over the n(max)2 1
begin
case choose is
when 0 >n n0
when 1 >n n1
when 2 >n n2
when 3 >n n3
when 4 >n n4
when 5 >n n5
when 6 >n n6
when 7 >n n7
when 8 >n n8
when 9 >n n9
when 10 >n n10
when 11 >n n11
when 12 >n n12
when 13 >n n13
when 14 >n n14
when 15 >n n15
when others > n n0
end case
if(clk＇event and clk＇1＇) then
if( count n2 1) then
temp < not temp
count 0
else
count count + 1
end if
end if
end process
sound_out < temp
end div_arch
2) 扫描信号发生电路
LIBRARY IEEE
USE IEEESTD_LOGIC_1164ALL
USE IEEESTD_LOGIC_ARITHALL
USE IEEESTD_LOGIC_UNSIGNEDALL
entity scan_seq is
produce the column scan signal
port( clkreset in std_logic
col out std_logic_vector(3 downto 0)
)
end scan_seq
architecture arch of scan_seq is
begin
process(clk)
variable count integer range 0 to 3
M4 counterevery count output the porper impulse
begin
if( reset ＇1＇)then
count 0
elsif( clk＇event and clk＇1＇ )then
if( count 3)then
count 0
else
count count +1
end if
end if
case count is
when 0 > col<1110
when 1 > col<1101
when 2 > col<1011
when 3 > col<0111
end case
end process
end arch
3) 数码译码电路
LIBRARY IEEE
USE IEEESTD_LOGIC_1164ALL
USE IEEESTD_LOGIC_ARITHALL
USE IEEESTD_LOGIC_UNSIGNEDALL
ENTITY seg7_1H IS seg7 decoding
PORT(
a IN STD_LOGIC_VECTOR(3 DOWNTO 0) input
b OUT STD_LOGIC_VECTOR(6 DOWNTO 0) output
cat OUT STD_LOGIC_VECTOR(7 DOWNTO 0) selcect
)
END seg7_1H
ARCHITECTURE aa OF seg7_1H IS
signal temp std_logic_vector(3 downto 0)
BEGIN
process(a)
begin
CASE a IS b60 > abcdefg
WHEN 0000 > b < 1111110 0
WHEN 0001 > b < 0110000 1
WHEN 0010 > b < 1101101 2
WHEN 0011 > b < 1111001 3
WHEN 0100 > b < 0110011 4
WHEN 0101 > b < 1011011 5
WHEN 0110 > b < 1011111 6
WHEN 0111 > b < 1110000 7
WHEN 1000 > b < 1111111 8
WHEN 1001 > b < 1111011 9
WHEN 1010 > b < 1110111 A
WHEN 1011 > b < 0011111 b
WHEN 1100 > b < 1001110 C
WHEN 1101 > b < 0111101 d
WHEN 1110 > b < 1001111 E
WHEN 1111 > b < 1000111 F
WHEN others > b < 0000000 others
END CASE
end process
cat < 11111110
END aa
4) 顶层
LIBRARY IEEE
USE IEEESTD_LOGIC_1164ALL
USE IEEESTD_LOGIC_ARITHALL
USE IEEESTD_LOGIC_UNSIGNEDALL
entity scanKeyboard is
scan the keyboard and display sound at the same time
port(
clkreset in std_logic
row in std_logic_vector(3 downto 0)
col out std_logic_vector(3 downto 0)
sound out std_logic
b out std_logic_vector(6 downto 0)
cat out std_logic_vector(7 downto 0)
seeclk out std_logic
)
end scanKeyboard
architecture arch of scanKeyboard is
component divide_sound is
the origin clk is 50MHz
divide the frequency to 1n
generic( n0natural4
n1natural8
n2natural12
n3natural16
n4natural20
n5natural24
n6natural28
n7natural42
n8natural46
n9natural50
n10natural54
n11natural58
n12natural62
n13natural66
n14natural70
n15natural74
)
port( clk in std_logic
choose in integer range 0 to 15
sound_out out std_logic
)
end component
component scan_seq is
produce the column scan signal
port( clkreset in std_logic
col out std_logic_vector(3 downto 0)
)
end component
component seg7_1H IS seg7 decoding
PORT(
a IN STD_LOGIC_VECTOR(3 DOWNTO 0) input
b OUT STD_LOGIC_VECTOR(6 DOWNTO 0) output
cat OUT STD_LOGIC_VECTOR(7 DOWNTO 0) selcect
)
END component
component divide is
divide the frequency to 1n
generic( nnatural200)
port( clk in std_logic
clk_out out std_logic)
end component
clk_scan is the scan signal for column
tempSound is the output of the sound divider
tempSegin is the input of the seg7 translate part
clock_change is disgned to record the row＇s impulse appear
choose is the select of the keyboard
signal clk_scan std_logic
signal tempSoundstd_logic
signal tempSeginstd_logic_vector(3 downto 0)
signal clock_changestd_logic
signal choose integer range 0 to 15
type state is (s0s1s2s3)
signal presentstate nextstate state
begin
u0divide_sound port map(clk > clkchoose>choosesound_out>tempSound)
u1divide port map(clk >clk clk_out>clk_scan)
u2scan_seq port map(clk>clk_scanreset>resetcol>col)
u3seg7_1H port map(a>tempSeginb>bcat>cat)
discrible the register for clk_scan
p1_regprocess(clk_scanreset)
begin
if(reset ＇1＇)then
presentstate< s0
elsif( clk_scan＇event and clk_scan＇1＇ )then
presentstate< nextstate
end if
end process
discrible the state for clk_scan
p2_stateChangeprocess(presentstate)
begin
case presentstate is
when s0 > nextstate< s1
when s1 > nextstate< s2
when s2 > nextstate< s3
when s3 > nextstate< s0
end case
end process
discrible the output
p3_outprocess(presentstaterowclock_change)
begin
behave synchronize with the clock_change
if( clock_change＇event and clock_change ＇1＇)then
case presentstate is
column[0]
when s0 > case row is
when 1110>
choose < 12
tempSegin < 1100
when 1101>
choose < 8
tempSegin < 1000
when 1011>
choose < 4
tempSegin < 0100
when 0111>
choose < 0
tempSegin < 0000
when others>
choose < 0
tempSegin < tempSegin
end case
column[1]
when s1 > case row is
when 1110>
choose < 13
tempSegin < 1101
when 1101>
choose < 9
tempSegin < 1001
when 1011>
choose < 5
tempSegin < 0101
when 0111>
choose < 1
tempSegin < 0001
when others >
choose < 0
tempSegin < tempSegin
end case
column[2]
when s2 > case row is
when 1110>
choose < 14
tempSegin < 1110
when 1101>
choose < 10
tempSegin < 1010
when 1011>
choose < 6
tempSegin < 0110
when 0111>
choose < 2
tempSegin < 0010
when others>
choose < 0
tempSegin < tempSegin
end case
column[3]
when s3 > case row is
when 1110>
choose < 15
tempSegin < 1111
when 1101>
choose < 11
tempSegin < 1011
when 1011>
choose < 7
tempSegin < 0111
when 0111>
choose < 3
tempSegin < 0011
when others>
choose < 0
tempSegin < tempSegin
end case
end case
end if
end process
discrible clkchange
p3_clkchangeprocess(row)
begin
if( row 1111)then
clock_change <＇0＇
else
clock_change<＇1＇
end if
end process
output the sound signal
sound < tempSound and clock_change
to see the clock_change in waveform
seeclk < clock_change
end arch
4 仿真波形分析
1) 分频器1（扫描时钟分频器）
图11分频器整体
图12 分频器计数99翻转（高翻低）
图13 分频器计数99翻转（低翻高）
实际应采分频50k现仿真时方便仿真取200分频图11整体分频情况图12分频器计数99时高电翻低电图13分频器计数99时低电翻高电
2) 分频器2（蜂鸣器提供频率分频器）
图21（a） 分频器整体图
图21（b）分频器整体图
图21（c）分频器整体图
图22（a） 分频器细节图n950
图22（b） 分频器细节图n950
仿真时扫描时钟信号200分频时钟信号蜂鸣器提供信号分频系数实际分频系数图21（a）（b）输出信号频率受输入choose信号控制choose增输出信号分频越设计符号先取中状态进行说明choose9nn950应计数器应记24然实现翻转图22（a）计数信号计数001100024实现低电翻高电图22（b）计数信号计数0011000实现高电翻低电完成控分频器
3) 扫描信号发生电路
图31扫描信号细节图
图32 扫描信号reset发生
图4知红框中序脉周期countcol输出应关系
count
col[i]0中i取值
00
0
01
1
10
2
11
3
实现序负脉发生器功时reset信号加入时count重新00开始计数序脉col[0]开始输出低电
4) 数码译码电路
图41（a）数码译码波形图
图42（b）数码译码波形图
图41（a）译码电路09译码说已较熟悉赘述现选取1015进行说明数码结构图图43示a101010应输出写A应abcefg应点亮d熄灭波形图中见输出b1110111设计相应a101111应输出写b应ab熄灭余点亮波形图中见b0011111设计相应a1100应输出写C应bcg熄灭余点亮波形图见b1001110设计相应
a1101应输出写d应af熄灭余点亮波形图见b0111101设计相应a1110时应输出写E应bc熄灭波形图见b1001111设计相应a1111时应输出写F应bcd熄灭波形图见b1000111设计相应波形图应译码起表示表1中位选信号catcat[0]显示位数码
图43 数码部结构图
表1：
计数信号
数码显示控制信号
0000
1111110
0001
0110000
0010
1101101
0011
1111001
0100
0110011
0101
1011011
0110
1011111
0111
1110000
1000
1111111
1001
1111011
1010
1110111
1011
0011111
1100
1001110
1101
0111101
1110
1001111
1111
1000111
5) 综合
图51 整体波形图
图52（a）整体波形图细节reset
图52（b）整体波形图细节（键1）
图52（c）整体波形图细节（键6）
图52（d）整体波形图细节（键910数码保持次）
图52（e）整体波形图细节（键12连续键）
图51键进行仿真（键0>15）整体出应键应tempSegin保障数码输出前键应值时12连续键波形图中时tempSegin持续12
图52（b）col[1]0row[3]0时应键1时输出蜂鸣器键相宽度信号时译码电路传入tempSegin1次键前保持tempSegin1时b01100001应译码
图53（c）col[2]0row[2]0时应键6时输出蜂鸣器键宽度相信号时频率键频率区时译码电路传入tempSegin6次键前保持tempSegin6时b10111116应译码
图54（d）键9时数码译码电路输入tempSeg9保持次键10
图54（e）键12连续时直数码译码电路输入 tempSeg12时直蜂鸣器输出相频率信号直键松开输出蜂鸣器信号保持数码显示信号
实验5点阵载验证图
— END —
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